The present invention relates generally to the field of integrated circuit processing, and more particularly relates to an FeRAM structure and a method of manufacture thereof having a bottom electrode diffusion barrier that avoids a substantial undercut thereof during formation of the FeRAM capacitor.
Several trends exist, today, in the semiconductor device fabrication industry and the electronics industry. Devices are continuously getting smaller and smaller and requiring less and less power. A reason for this is that more personal devices are being fabricated which are very small and portable, thereby relying on a small battery as its supply source. For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market. In addition to being smaller and more portable, personal devices are requiring more computational power and on-chip memory. In light of all these trends, there is a need in the industry to provide a computational device that has a fair amount of memory and logic functions integrated onto the same semiconductor chip. Preferably, this memory will be configured such that if the battery dies, the contents of the memory will be retained. Such a memory device that retains its contents while a signal is not continuously applied to it is called a non-volatile memory. Examples of conventional non-volatile memory include: electrically erasable, programmable read only memory (xe2x80x9cEEPROMxe2x80x9d) and FLASH EEPROM.
A ferroelectric memory (FeRAM) is a non-volatile memory that utilizes a ferroelectric material, such as SBT or PZT, as the capacitor dielectric situated between a bottom electrode and a top electrode. Both read and write operations are performed for a FeRAM. The memory size and memory architecture affect the read and write access times of a FeRAM. Table 1 illustrates the differences between different memory types.
The non-volatility of an FeRAM is due to the bi-stable-characteristic of the ferroelectric memory cell. Two types of memory cells are used, a single capacitor memory cell and a dual capacitor memory cell. The single capacitor memory cell (referred to as a 1 T/1 C or 1 C memory cell) requires less silicon area (thereby increasing the potential density of the memory array), but is less immune to noise and process variations. Additionally, a 1 C cell requires a voltage reference for determining a stored memory state. The dual capacitor memory cell (referred to as a 2 T/2 C or 2 C memory cell) requires more silicon area, and it stores complementary signals allowing differential sampling of the stored information. The 2 C memory cell is more stable than a 1 C memory cell.
As illustrated in prior art FIG. 1, a 1 T/1 C FeRAM cell 10 includes one transitor 12 and one ferroelectric storage capacitor 14. A bottom electrode of the storage capacitor 14 is connected to a drain terminal 15 of the transistor 12. The 1 T/1 C cell 10 is read from by applying a signal to the gate 16 of the transistor (word line WL)(e.g., the Y signal), thereby connecting the bottom electrode of the capacitor 14 to the source of the transistor (the bit line BL) 18. A pulse signal is then applied to the top electrode contact (the plate line or drive line DL) 20. The potential on the bit line 18 of the transitor 12 is, therefore, the capacitor charge divided by the bit line capacitance. Since the capacitor charge is dependent upon the bi-stable polarization state of the ferroelectric material, the bit line potential can have two distinct values. A sense amplifier (not shown) is connected to the bit line 18 and detects the voltage associated with a logic value of either 1 or 0. Frequently the sense amplifier reference voltage is a ferroelectric or non-ferroelectric capacitor connected to another bit line that is not being read. In this manner, the memory cell data is retrieved.
A characteristic of the shown ferroelectric memory cell is that a read operation is destructive. The data in a memory cell is then rewritten back to the memory cell after the read operation is completed. If the polarization of the ferroelectric is switched, the read operation is destructive and the sense amplifier must rewrite (onto that cell) the correct polarization value as the bit just read from the cell. This is similar to the operation of a DRAM. The one difference from a DRAM is that a ferroelectric memory cell will retain its state until it is interrogated, thereby eliminating the need of refresh.
As illustrated, for example, in prior art FIG. 2, a 2 T/2 C memory cell 30 in a memory array couples to a bit line 32 and an inverse of the bit line (xe2x80x9cbit line-barxe2x80x9d) 34 that is common to many other memory types (for example, static random access memories). Memory cells of a memory block are formed in memory rows and memory columns. The dual capacitor ferroelectric memory cell comprises two transistors 36 and 38 and two ferroelectric capacitors 40 and, 42, respectively. The first transistor 36 couples between the bit line 32 and a first capacitor 40, and the second transistor 38 couples between the bit line-bar 34 and the second capacitor 42. The first and second capacitors 40 and 42 have a common terminal or plate (the drive line DL) 44 to which a signal is applied for polarizing the capacitors.
In a write operation, the first and second transistors 36 and 38 of the dual capacitor ferroelectric memory cell 30 are enabled (e.g., via their respective word line 46) to couple the capacitors 40 and 42 to the complementary logic levels on the bit line 32 and the bar-bar line 34 corresponding to a logic state to be stored in memory. The common terminal 44 of the capacitors is pulsed during a write operation to polarize the dual capacitor memory cell 30 to one of the two logic states.
In a read operation, the first and second transistors 36 and 38 of the dual capacitor memory cell 30 are enabled via the word line 46 to couple the information stored on the first and second capacitors 40 and 42 to the bar 32 and the bit line-bar line 34, respectively. A differential signal (not shown) is thus generated across the bit line 32 and the bit line-bar line 34 by the dual capacitor memory cell 30. The differential signal is sensed by a sense amplifier (not shown) that provides a signal corresponding to the logic level stored in memory.
A memory cell of a ferroelectric memory is limited to a finite number of read and write operations before the memory cell becomes unreliable. The number of operations that can be performed on a FeRAM memory is known as the endurance of a memory. The endurance is an important factor in many applications that require a nonvolatile memory. Other factors such as memory size, memory speed, and power dissipation also play a role in determining if a ferroelectric memory is viable in the memory market.
In essence, the instant invention relates to the fabrication of an FeRAM device which is either a stand-alone device or one which is integrated onto a semiconductor chip which includes many other device types. Several requirements either presently exist or may become requirements for the integration of FeRAM with other device types. One such requirement involves utilizing, as much as possible, the conventional front end and back end processing techniques used for fabricating the various logic and analog devices on the chip to fabricate this chip which will include FeRAM devices. In other words, it is beneficial to utilize as much of the process flow for fabricating these standard logic devices (in addition to I/O devices and potentially analog devices) as possible, so as not to greatly disturb the process flow (and thus increase the process cost and complexity) merely to integrate the FeRAM devices onto the chip.
The following discussion is based on the concept of creating the ferroelectric capacitors in a FeRAM process module that occurs between the front end module (defined to end with the formation of W contacts) and the back end process module (mostly metallization). Other locations of the FeRAM process module have also been proposed. For example, if the FeRAM process module is placed over the first layer of metallization then a capacitor over bar structure can be created with the advantage that a larger capacitor can be created. One disadvantage of the approach is that either Metal-1 or a local interconnect must be compatible with FeRAM process temperature (W for example) or the FeRAM process temperature must be lowered to be compatible with standard metallization (Alxcx9c450 C, Cu-Low-Kxcx9c400 C). This location has some advantages for commodity memory purposes, but has cost disadvantages for embedded memory applications. Another proposed location for the FeRAM process module is near the end of the back end process flow. The principal advantage of this approach is that it keeps new contaminants in the FeRAM module (Pb, Bi, Zr, Ir, Ru, or Pt) out of more production tools. This solution is most practical if the assumption is that all of the equipment used after deposition of the first FeRAM film must be dedicated and can not be shared. This solution has the drawback of requiring FeRAM process temperatures compatible with standard metallization plus wiring of the FeRAM capacitor to transistor and other needs of metallization are not compatible with a minimum FeRAM cell size.
The requirements for the other locations will have many of the same concerns, but some requirements will be different.
The FeRAM process module must therefore be compatible with front-end process flow including the use of W contacts (currently standard in most logic flows) as the bottom contact of the capacitor. The FeRAM thermal budget must also be low enough so that it does not impact the front-end structures such as the low resistance structures (such as tungsten plugs and silicided source/drains and gates) required by most logic devices. In addition, transistors and other front-end devices such as diodes are sensitive to contamination and the FeRAM process module can not contaminate these devices either directly (diffusion in chip) or indirectly (cross contamination through shared equipment). The FeRAM devices and process module must also be compatible with a standard back end process flow. Therefore the FeRAM process module must have minimum degradation of logic metallization""s resistance and parasitic capacitance between metal and transistor. In addition, the FeRAM devices must not be degraded by the back end process flow with minimal, if any, modification. This is a significant challenge since ferroelectric capacitors have been shown to be sensitive to hydrogen degradation and most logic back end process flows use hydrogen/deuterium in many of the processes (SiO2, Si3N4, and CVD W deposition, SiO2 via etch, and forming gas anneals).
Commercial success of FeRAM also requires minimization of embedded memory cost. Total memory cost is primarily dependent on cell size, periphery ratio size, impact of yield, and additional process costs associated with memory. In order to have a cost advantage per bit compared to standard embedded memories such as embedded DRAM and Flash it is necessary to have cell sizes that are not much larger than these competing technologies. Some of the methods discussed in this patent to minimize cell size is to make the process flow less sensitive to lithography misalignment, have the capacitor directly over the contact, and using a single mask for the capacitor stack etch.
In accordance with one aspect of the present invention, a method of forming an FeRAM capacitor is provided in which a TiAlON bottom electrode diffusion barrier layer is employed. The inventors of the present invention discovered that a prior art TiAlN barrier is a source of integration problems during subsequent processing of the FeRAM capacitor. More particularly, it was discovered that during subsequent processing of the FeRAM capacitor stack (via etching), an etching of the TiAlN barrier layer between neighboring FeRAM capacitor cells caused a substantial undercutting of the TiAlN beneath the capacitor stack and such phenomena negatively contributed to poor step coverage of a subsequently formed electrically insulating FeRAM sidewall diffusion barrier. Consequently, the overall diffusion barrier (top, bottom and sidewalls) of the FeRAM capacitor is compromised.
The inventors of the present invention, having appreciated the above problem with the prior art, overcome the difficulties associated therewith by replacing the TiAlN barrier layer with a TiAlON barrier layer. Such a replacement, however, is not a mere substitution of another material because one of ordinary skill in the art would not be motivated to add oxygen in such a layer because such an addition increases the electrical resistance of the resulting layer. The inventors of the present invention, however, discovered that by adding a small amount of oxygen, one could obtain a substantial reduction in the isotropy of the chlorine etch without substantially increasing a resistivity of the barrier layer, that is, increasing the resistivity above a predetermined level.
According to one exemplary aspect of the present invention, the composition of the TiAlON is tuned to provide sufficient aluminum therein for adequate oxidation resistance (of the underlying tungsten contact(s)) and enough oxygen to prevent undercutting during an etch thereof, yet concurrently maintaining the resistivity thereof low enough to prevent any appreciable degradation of the electrical performance of the circuit. In one example, the aluminum composition is at least about 20 cation atom %, and less than about 50 cation atom %; and the oxygen composition is at least about 5 anion atom %, and less than about 50 anion atom %. In another example, the aluminum composition is at least about 35 cation atom %, and less than about 45 cation atom %; and the oxygen composition is at least about 10 anion atom %, and less than about 20 anion atom %.
In accordance with one exemplary aspect of the present invention, it is desirable to have a barrier resistivity of about 4300 xcexcxcexa9-cm or less. Therefore in tailoring the TiAlON film, it is desired to keep the amount of oxygen therein sufficiently low such that the resistivity does not exceed substantially the 4300 xcexcxcexa9-cm figure. For example, with a TiAlON content of about Ti≈0.5, Al≈0.4, O≈0.1, and N≈0.9, a film resistivity of about 1800 xcexcxcexa9-cm was obtained.
In accordance with another aspect of the present invention, a new hard mask structure is disclosed. The inventors of the present invention discovered that when a single layer hard mask was employed that was the same or similar material to that of the bottom electrode diffusion barrier, an etch of the bottom electrode diffusion barrier resulted in substantial degradation to the hard mask, for example, corner rounding, that caused a potential exposure of the underlying top electrode, thereby providing the potential for contamination. Accordingly, a multi-layer hard mask is disclosed in which a hard masking layer overlies an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.
In addition, in accordance with another aspect of the present invention, the etch stop layer is electrically conductive and serves as a diffusion barrier, thereby eliminating a need for another diffusion barrier layer and reducing an overall height of the FeRAM capacitor stack.
In accordance with another aspect of the present invention, a sidewall diffusion barrier layer deposition and selective removal thereof is disclosed. The inventors of the present invention discovered that the prior art formation and selective removal of the sidewall diffusion barrier layer had several disadvantages associated therewith. For example, it was discovered in such a solution since AlOx (a common sidewall diffusion barrier material) is not substantially selective with respect to the underlying interlayer dielectric, typically SiO2, the selective removal of the AlOx between capacitor stacks aggressively attacked the underlying interlayer dielectric. In addition, if either the hard mask or the bottom electrode diffusion barrier layer comprise a nitride containing sufficient oxygen content (e.g., TiAlON with high O content), the AlOx etch would also attack such layers and in some cases compromise the top/bottom barrier capability of such layers. Accordingly, the inventors appreciating the problems associated with the prior art, disclose a method of forming and selectively patterning the sidewall diffusion barrier layer over the capacitor stack before the etching of the bottom electrode diffusion barrier layer.
In accordance with another aspect of the present invention, a method of patterning the sidewall diffusion barrier layer prior to etching the underlying bottom electrode diffusion barrier layer is provided. According to one exemplary aspect, the etch chemistry for etching the AlOx sidewall diffusion barrier is BCl3+Ar. The BCl3 is effective in etching the AlOx with a good selectivity to the underlying nitride hard mask on top of the capacitor stack (e.g., TiAlN) and nitride bottom electrode diffusion barrier (e.g., TiAlON with small oxygen content) between the neighboring capacitor stacks. The Ar may be added to the etch chemistry because the resulting surface (of a top portion of the hard mask and the bottom electrode diffusion barrier) is smoother.
This type of etch process would potentially cause problems if the etch back of the sidewall diffusion barrier layer was performed after etching the TiAlN bottom electrode diffusion barrier because it quickly etches SiO2 (also an oxide). However, in accordance with the present invention, since the AlOx sidewall diffusion barrier etch is performed prior to the etch of the bottom electrode diffusion barrier, no such problem occurs.
In addition, the BCl3 etch is substantially selective with respect to the underlying nitride layers (the hard mask and the bottom electrode diffusion barrier layer). The aluminum-oxygen bonds in the AlOx layer are extremely strong, however, the boron in the BCl3 reacts with oxygen to break the aluminum-oxygen bonds. The chlorine in the BCl3 then reacts with the aluminum to remove the AlOx. After the AlOx is removed, the boron in the BCl3 reacts with nitrogen in the underlying nitrides to form boron nitride, which slows down subsequent etching. Therefore, one can perform a substantial overetch of the AlOx sidewall diffusion barrier layer without substantially impacting the nitrides underneath (e.g., TiAlN or TiAlON (low content O) masking layer or bottom electrode diffusion barrier). This is particularly helpful with regard to the bottom electrode diffusion barrier layer since it allows the AlOx sidewall diffusion barrier to be completely removed thereover, thus ensuring that all of the underlying bottom electrode diffusion barrier is exposed for removal in a subsequent etch process, and thus ensuring that the neighboring capacitor stacks are electrically isolated from one another.
In accordance with yet another aspect of the present invention, a method of ascertaining whether a sidewall diffusion barrier is sufficiently thick on the sidewalls of the capacitor stack to provide an effective hydrogen barrier is disclosed. It is desirable to remove the sidewall diffusion barrier layer off of the top of the capacitor stack and in the areas between the stacks; however, it is desirable for the sidewall diffusion barrier to remain on the stack sidewalls in order to protect the ferroelectric dielectric in the stack from hydrogen contamination. Because the capacitor stack is not perfectly vertical and since the etch thereof has a chemical component, the sidewall diffusion barrier layer on the sidewalls does get etched to some degree and often it is desirable to analyze the capacitor stack after the sidewall barrier etch to ensure that the barrier still covers the capacitor stack sidewalls. Because the remaining sidewall layer may be relatively thin, however, analyzing the sidewall layer is difficult.
The inventors of the present invention discovered that if the thickness of the masking layer portion of the hard mask is sufficiently thick, during the capacitor stack etch, although rounding will be experienced at the corners thereof, the sidewall diffusion barrier layer will overlie such corners upon its deposition. Subsequently, during the etch of the masking layer portion of the hard mask (which will typically be done concurrently with an etch of the bottom electrode diffusion barrier layer), a portion of the sidewall diffusion barrier layer overlying a corner portion of the masking layer will protect such portion of the masking layer from being etched, thereby resulting in xe2x80x9cearsxe2x80x9d being formed on top of the hard mask etch stop layer. Note, however, if a thickness of the sidewall diffusion barrier layer is not sufficiently thick, no portion will overlie the masking layer 306, and consequently no xe2x80x9cearsxe2x80x9d will form. Therefore by evaluating a capacitor stack after the etching of the masking layer, identification of the xe2x80x9cearsxe2x80x9d allows one to quickly ascertain that the sidewall diffusion layer is adequately covering the capacitor stack sidewalls.
To the accomplishment of the foregoing and related ends, the invention comprises the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative, however, of but a few of the various ways in which the principles of the invention may be employed. Other objects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.